Commit Graph

19 Commits

Author SHA1 Message Date
c66cf7a947 Add measured FTPO speedup numbers from the max_seq_length fix
Ran a 30-minute validation with finetune_max_seq_length=1280 to confirm the
predicted speedup from the previous commit. Measured ~40s/step steady-state
(vs ~160-185s/step at max_seq_length=4000) -- a ~4.3x speedup, better than
the ~3x predicted from the token-count ratio alone. Extrapolated full-run
ETA drops from ~34h to ~8.3h. No errors across the validation run.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
2026-08-08 10:31:30 -05:00
cbd88aa758 Correct FTPO slowness diagnosis: fixed-length padding, not compute-bound
Measured actual FTPO training context lengths (real tokenizer, all 12,000
examples): mean 530 tokens, p99 1080, max 1126 -- against a configured
finetune_max_seq_length of 4000. ftpo_trainer.py's collator pads every batch
to that fixed length rather than to the longest sequence in the batch, so
every forward pass was processing ~4000 tokens of mostly padding (~13%
utilization on average). This also explains why batch_size 1->4 had no
effect: total padded-token compute is invariant to the batch/accum split.

Lowered finetune_max_seq_length to 1280 (covers p99 with headroom, nothing
in the dataset gets truncated) -- should cut per-step compute roughly 3x.
Updated DGX_SPARK_SETUP.md §7 with the measurement and corrected takeaway.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
2026-08-08 09:57:03 -05:00
4edb2135be Add DGX Spark (aarch64/Blackwell) setup fixes and documentation
- utils/vllm_manager.py: drop --disable-log-requests, removed in vLLM 0.26.0
- core/ftpo_trainer.py: pass token_type_ids to the 3 model forward calls in
  compute_loss -- transformers 5.5.0's Gemma3 requires it during training
  for causal-mask construction (Gemma3 is natively multimodal)
- configs/gemma-3-4b-it.yaml: lower vllm_gpu_memory_utilization 0.85->0.5,
  since the DGX Spark's 121GB is unified CPU/GPU memory and the default
  starved the OS, causing swap thrashing
- DGX_SPARK_SETUP.md: full writeup of the above plus the parts that don't
  live in this repo (two-conda-env split to resolve a vllm/unsloth
  transformers version conflict, flash-attn source build flags, torch/CUDA
  version matching, ~/.triton/cache permissions)

The antislop-vllm submodule also needed a one-line fix (removing an invalid
reference_compile kwarg in utils/refusal_detector.py that was silently
disabling refusal filtering) -- documented in DGX_SPARK_SETUP.md rather than
committed as a submodule pointer change, since we don't have push access to
upstream's antislop-vllm repo.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
2026-08-08 07:39:37 -05:00
sam-paech
da2231574f Fix overrepresented word quota spill 2026-07-28 20:44:19 -07:00
sam-paech
bc9e75fdec Fix chosen-token regularization 2026-07-23 15:42:54 -07:00
sam-paech
6299030455 update antislop-vllm submodule 2026-07-18 21:59:11 -07:00
sam-paech
8fb98fdf01 gemma 4 fixes 2026-04-25 01:39:11 +10:00
sam-paech
a652a819ae fix for tokeniser compat 2026-04-24 22:30:59 +10:00
sam-paech
8540f32b21 update antislop-vllm 2026-04-24 21:39:00 +10:00
sam-paech
adf87c2a0a ftpo fixes 2026-04-24 21:03:24 +10:00
sam-paech
7b8e3217e1 fix for custom lists not being used at antislop generation phase 2025-11-07 23:53:02 +11:00
sam-paech
c7e92a4516 fix extra phrases not being merged 2025-11-03 15:32:56 +11:00
sam-paech
af04bf4d74 cleanup 2025-10-25 14:45:21 +11:00
sam-paech
c5914c077f add link to preprint 2025-10-24 15:04:56 +11:00
sam-paech
30f16946b4 update readme 2025-10-24 14:55:39 +11:00
sam-paech
8b4b270806 ensure submodule dirs are present and non-empty 2025-10-17 03:49:09 +11:00
sam-paech
9410c4c675 warn if submodules missing 2025-10-17 03:46:24 +11:00
sam-paech
b480cb72f7 initial upload 2025-10-17 03:44:24 +11:00
sam-paech
49cff43c50 initial upload 2025-10-17 03:44:22 +11:00